The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Jun. 12, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hari V. Mallela, Poughquag, NY (US);

Reinaldo A. Vega, Mahopac, NY (US);

Rajasekhar Venigalla, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823456 (2013.01); H01L 21/823412 (2013.01); H01L 21/823468 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 21/82385 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823885 (2013.01);
Abstract

A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.


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