The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Oct. 05, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Cheng-Hong Wei, Taichung, TW;

Hung-Sheng Chen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 21/3065 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/0274 (2013.01); H01L 21/3065 (2013.01); H01L 21/32139 (2013.01); H01L 23/544 (2013.01); H01L 2223/54426 (2013.01);
Abstract

A manufacturing method of a semiconductor chip is provided. The method includes: forming a first metal pattern over a substrate and within a chip region and a scribe line region of the substrate, wherein the chip region is surrounded by the scribe line region; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all portions of the metal material layer within the scribe line region and a portion of the metal material layer within the chip region, so as to form a second metal pattern within the chip region; forming a third metal pattern, wherein the second metal pattern within the chip region is covered by the third metal pattern, and the third metal pattern is located over the first metal pattern within the scribe line region; and performing singulation along the scribe line region, to form the semiconductor chip.


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