Memory and operation method thereof

Abstract

A memory is disclosed. A memory cell comprises three gate structures sequentially arrayed between a first source-drain region and a second source-drain region. A first gate structure and a third gate structure are formed by superposition of a first gate dielectric layer, a floating gate, a second gate dielectric layer and a polysilicon control gate, so that two memory bits and two control gates are formed. A second gate structure is located between the first gate structure and the third gate structure and serves as a select gate. Erasing and programming operations on the two memory bits formed by the floating gates are realized by FN tunneling. During erasing and programming, the first source-drain region and the second source-drain region are grounded, so that the memory bits can be selected and then erased or programmed only by controlling voltages of the first control gate, the select gate and the second control gate. An operation method of a memory is further disclosed. The two memory bits of the memory cell can be independently operated, so that operations on single memory bits are achieved, and accordingly, storage-computation integrated operations are realized.