Multi-level cell (mlc) techniques and circuits for cross-point memory

Abstract

Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a third read voltage with a greater magnitude is applied across the memory cell. In one example, the thresholding of the memory cell triggers the application of a write current to write back the state of the bit due to read disturb from the read.