The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Mar. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kaladhar Radhakrishnan, Gilbert, AZ (US);

Jaejin Lee, Beaverton, OR (US);

Hao-Han Hsu, Portland, OR (US);

Chung-Hao J. Chen, Portland, OR (US);

Dong-Ho Han, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 23/552 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2006.01); H05K 1/18 (2006.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/4803 (2013.01); H01L 21/4846 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/645 (2013.01); H01L 23/66 (2013.01); H01L 25/18 (2013.01); H01L 28/10 (2013.01); H05K 1/181 (2013.01); H05K 1/183 (2013.01); H01L 2223/6661 (2013.01); H01L 2223/6666 (2013.01); H05K 2201/086 (2013.01); H05K 2201/09072 (2013.01);
Abstract

Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.


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