The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Mar. 06, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wei-Chih Chuang, Tainan, TW;

Chia-Jong Liu, Ping-Tung County, TW;

Kuang-Hsiu Chen, Tainan, TW;

Chung-Ting Huang, Kaohsiung, TW;

Chi-Hsuan Tang, Kaohsiung, TW;

Kai-Hsiang Wang, Taichung, TW;

Bing-Yang Jiang, Tainan, TW;

Yu-Lin Cheng, Changhua County, TW;

Chun-Jen Chen, Tainan, TW;

Yu-Shu Lin, Pingtung County, TW;

Jhong-Yi Huang, Nantou County, TW;

Chao-Nan Chen, Tainan, TW;

Guan-Ying Wu, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 29/42364 (2013.01);
Abstract

A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.


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