The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Nov. 15, 2019
Applicant:

Shanghai Huali Microelectronics Corporation, Shanghai, CN;

Inventors:

Li He, Shanghai, CN;

Xiaohua Ju, Shanghai, CN;

Guanqun Huang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/033 (2006.01); H01L 27/115 (2017.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0337 (2013.01); H01L 21/0332 (2013.01); H01L 22/12 (2013.01); H01L 27/115 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01);
Abstract

The present invention provides a method for optimizing a critical dimension for double patterning for NAND flash, forming a core oxide layer on amorphous silicon layer on substrate; densifying the core oxide layer and etching it to form a core pattern; measuring CD values of the bottom and top of the core pattern; providing etching rates of a non-densified core oxide layer and a densified core oxide layer under the same etching condition; calculating the thickness of the core oxide layer required to be densified according to the CD values of the bottom and top of the core pattern and the etching rates to determine the densifying time. The present invention precisely controls the morphology and CD, and obtains a double-patterned target pattern with consistent CD sizes of a top and a bottom and a consistent bottom height, so as to improve a product yield.


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