The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Jul. 03, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Dale H. Hiscock, Boise, ID (US);

Michael Kaminski, Boise, ID (US);

Joshua E. Alzheimer, Boise, ID (US);

John H. Gentry, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 7/22 (2006.01); G11C 11/408 (2006.01); G11C 11/4076 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 5/148 (2013.01); G11C 7/222 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01);
Abstract

Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.


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