The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Dec. 21, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Lien Huang, Jhubei, TW;

Chun-Hsiang Fan, Hsinchu, TW;

Tung Ying Lee, Hsin-Chu, TW;

Chi-Wen Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 29/12 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); H01L 29/045 (2013.01); H01L 29/122 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/66666 (2013.01); H01L 29/66795 (2013.01); H01L 29/66977 (2013.01); H01L 29/7827 (2013.01);
Abstract

FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.


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