The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Jun. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Dipanjan Basu, Hillsboro, OR (US);

Seung Hoon Sung, Portland, OR (US);

Glenn A. Glass, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.


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