The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

May. 21, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Scott J. Derner, Boise, ID (US);

Michael Amiel Shore, Boise, ID (US);

Charles L. Ingalls, Meridian, ID (US);

Steve V. Cole, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 27/108 (2006.01); G11C 11/408 (2006.01); H01L 49/02 (2006.01); G11C 11/4097 (2006.01); H01L 29/08 (2006.01); G11C 11/4094 (2006.01); G11C 5/02 (2006.01); G11C 11/403 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
H01L 27/108 (2013.01); G11C 5/025 (2013.01); G11C 11/403 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); H01L 28/90 (2013.01); H01L 29/0847 (2013.01); G11C 11/4091 (2013.01); H01L 28/86 (2013.01);
Abstract

Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.


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