The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Jul. 26, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Jaspreet Singh Gandhi, San Jose, CA (US);

Tien-Yu Lee, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/27 (2013.01); H01L 24/83 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/14 (2013.01);
Abstract

An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.


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