Maskless epitaxial growth of phosphorus-doped si and boron-doped sige (ge) for advanced source/drain contact

Abstract

A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.