The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Jan. 27, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Dave Jefferson, Morgan Hill, CA (US);

C. Omar Benitez, Meridian, ID (US);

Yoshinori Fujiwara, Boise, ID (US);

Christopher S. Wieduwilt, Boise, ID (US);

Vivek Kotti, Boise, ID (US);

Dennis G. Montierth, Meridian, ID (US);

Joshua E. Alzheimer, Boise, ID (US);

Daniel S. Miller, Boise, ID (US);

Kevin G. Werhane, Kuna, ID (US);

Jason M. Johnson, Nampa, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 29/08 (2006.01); G11C 7/22 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1006 (2013.01); G11C 7/22 (2013.01); G11C 29/08 (2013.01); G11C 29/70 (2013.01); G11C 29/88 (2013.01); G11C 29/883 (2013.01);
Abstract

Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.


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