The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Sep. 20, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Marcello Mariani, Milan, IT;

Anna Maria Conti, Milan, IT;

Sara Vigano, Monza, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11551 (2017.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/744 (2006.01); H01L 21/308 (2006.01); H01L 21/8249 (2006.01); H01L 29/66 (2006.01); H01L 21/8239 (2006.01); H01L 27/102 (2006.01); H01L 29/749 (2006.01); H01L 21/8229 (2006.01); H01L 21/8234 (2006.01); H01L 27/105 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/308 (2013.01); H01L 21/8229 (2013.01); H01L 21/8239 (2013.01); H01L 21/8249 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01); H01L 27/1022 (2013.01); H01L 27/1027 (2013.01); H01L 27/1052 (2013.01); H01L 29/4236 (2013.01); H01L 29/42364 (2013.01); H01L 29/66333 (2013.01); H01L 29/66363 (2013.01); H01L 29/66666 (2013.01); H01L 29/744 (2013.01); H01L 29/749 (2013.01); H01L 29/7827 (2013.01);
Abstract

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.


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