The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2021
Filed:
Oct. 03, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Mahesh A. Iyer, Fremont, CA (US);
Vasudeva M. Kamath, San Jose, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/3312 (2020.01); G06F 30/34 (2020.01); G06F 30/327 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/30 (2020.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01);
Abstract
A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the register retiming of registers in the system driven by a different clock.