The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Dec. 30, 2017
Applicant:

Spin Memory, Inc., Fremont, CA (US);

Inventors:

Kuk-Hwan Kim, San Jose, CA (US);

Dafna Beery, Palo Alto, CA (US);

Amitay Levi, Cupertino, CA (US);

Andrew J. Walker, Mountain View, CA (US);

Assignee:

SPIN MEMORY, INC., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 21/28 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 43/12 (2006.01); H01L 23/528 (2006.01); G11C 11/16 (2006.01); H01L 23/522 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 29/78 (2006.01); H01L 21/3065 (2006.01); H01L 29/423 (2006.01); H01F 10/32 (2006.01); H01L 29/66 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/161 (2013.01); H01F 10/329 (2013.01); H01F 10/3259 (2013.01); H01F 10/3272 (2013.01); H01F 10/3286 (2013.01); H01L 21/28158 (2013.01); H01L 21/3065 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/41741 (2013.01); H01L 29/42364 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01L 23/53271 (2013.01);
Abstract

According to one embodiment, a method includes forming a first insulative layer above a bottom surface of a groove and along inner sidewalls thereof, forming a source line layer within the groove of the substrate, forming a first dielectric layer on outer sides of a middle portion of the source line layer, forming a buffer layer on outer sides of the first dielectric layer, forming a gate terminal above the source line layer, forming a gate dielectric layer between the source line layer and the gate terminal and on outer sides of the lower portion of the gate terminal, forming a drain terminal including strained Si on outer sides of the first dielectric layer, and forming a relaxed buffer layer on outer sides of the upper portion of the source line layer and outer sides of the drain terminal, with the gate terminal extending beyond the relaxed buffer layer thickness.


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