The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2021
Filed:
Dec. 28, 2018
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventor:
Riichiro Shirota, Taichung, TW;
Assignee:
WINBOND ELECTRONICS CORP., Taichung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); H01L 21/28 (2006.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01);
Abstract
NOR flash memory that includes three-dimensional memory cells is provided. In the NOR flash memory of the present disclosure, one memory cell includes one memory transistor and one selection transistor. A common sourceis formed over a silicon substrate, and an active regionextending in a vertical direction to electrically connect to the common sourceis formed. A control gateof the memory transistor and a selection gate lineof the selection transistor are formed to surround a side portion of the active region, and a top portion of the active regionis electrically connected to a bit line