The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2021
Filed:
Mar. 27, 2019
Applied Materials, Inc., Santa Clara, CA (US);
He Ren, San Jose, CA (US);
Maximillian Clemons, Sunnyvale, CA (US);
Mei-Yee Shek, Palo Alto, CA (US);
Minrui Yu, Sunnyvale, CA (US);
Bencherki Mebarki, Santa Clara, CA (US);
Mehul B. Naik, San Jose, CA (US);
Chentsau Ying, Cupertino, CA (US);
Srinivas D. Nemani, Sunnyvale, CA (US);
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Abstract
Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.