The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Nov. 01, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Teng Liao, Hsin-Chu, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Chih Hsuan Cheng, Houlong Township, TW;

Li-Te Hsu, Shanhua Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/225 (2006.01); H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 29/08 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2255 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823814 (2013.01); H01L 21/823892 (2013.01); H01L 29/0847 (2013.01); H01L 29/66803 (2013.01); H01L 29/785 (2013.01); H01L 21/823481 (2013.01); H01L 21/823878 (2013.01);
Abstract

A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.


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