The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Jun. 25, 2018
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Wen-Shen Li, Singapore, SG;

Ching-Yang Wen, Pingtung County, TW;

Purakh Raj Verma, Singapore, SG;

Xingxing Chen, Singapore, SG;

Chee-Hau Ng, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/306 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76898 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 21/28518 (2013.01);
Abstract

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.


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