The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2021
Filed:
Oct. 18, 2018
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/3205 (2006.01); H01L 21/762 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); H01L 21/0223 (2013.01); H01L 21/26513 (2013.01); H01L 21/30625 (2013.01); H01L 21/32055 (2013.01); H01L 21/76224 (2013.01); H01L 27/0629 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01);
Abstract
Embodiments of a deep trench capacitor are disclosed. In one example a plurality of deep trenches is located in a first region of a semiconductor wafer, the first region having a first conductivity type. A corresponding dielectric layer is located on a surface of each of the plurality of deep trenches, and a corresponding doped polysilicon filler is located within each of the dielectric layers. Dielectric-filled trenches are located between each of the dielectric layers and the surface of the semiconductor wafer.