The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Sep. 16, 2019
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Xincheng Zhang, Shanghai, CN;

Jian An, Shanghai, CN;

Fangfang Li, Shanghai, CN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 119/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2119/06 (2020.01);
Abstract

Various embodiments provide for modeling a power and ground (PG) mesh for a circuit design placement process. For some embodiments, a reference PG mesh can be used to generate a PG mesh model for a circuit design. A PG mesh model can be generated for a circuit design by calculating how much routing resource is occupied by the reference PG mesh of the circuit design, and the resulting PG mesh model can be applied to the circuit design by removing a similar amount of routing resource from the circuit design during a placement circuit design flow. Additionally (or alternatively), a PG mesh model can be generated to comprise a set of metal obstructions that correspond to each macro of the circuit design, and the PG mesh model can be applied to the circuit design by adding the metal obstructions to one or more metal layers of the circuit design.


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