The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2021

Filed:

Sep. 28, 2017
Applicant:

Shinkawa Ltd., Tokyo, JP;

Inventors:

Tomonori Nakamura, Tokyo, JP;

Toru Maeda, Tokyo, JP;

Assignee:

SHINKAWA LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 21/44 (2006.01); H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 24/73 (2013.01); H01L 24/75 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 25/065 (2013.01); H01L 25/07 (2013.01); H01L 25/18 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/7555 (2013.01); H01L 2224/7565 (2013.01); H01L 2224/75252 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81986 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/83986 (2013.01); H01L 2224/92143 (2013.01);
Abstract

The disclosure is provided with: a temporary crimping step in which one or more semiconductor chipsare sequentially laminated while being temporarily crimped in each of two or more locations on a substrateto thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.


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