The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2021
Filed:
Jun. 17, 2019
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Balkrishna R. Rashingkar, San Jose, CA (US);
Leonardos J. van Bokhoven, Waalre, NL;
Peiqing Zou, San Jose, CA (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2119/18 (2020.01); Y02P 90/02 (2015.11);
Abstract
Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.