The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Jun. 10, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Rajesh N. Gupta, Karnataka, IN;

Farid Nemati, Redwood City, CA (US);

Scott T. Robins, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8249 (2006.01); H01L 27/102 (2006.01); H01L 29/735 (2006.01); H01L 29/73 (2006.01); H01L 21/02 (2006.01); H01L 21/8229 (2006.01); H01L 29/16 (2006.01); H01L 29/732 (2006.01); H01L 29/739 (2006.01); H01L 27/108 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1026 (2013.01); H01L 21/02381 (2013.01); H01L 21/02529 (2013.01); H01L 21/8229 (2013.01); H01L 27/1023 (2013.01); H01L 27/1024 (2013.01); H01L 29/1608 (2013.01); H01L 29/73 (2013.01); H01L 29/732 (2013.01); H01L 29/735 (2013.01); H01L 29/7391 (2013.01); H01L 27/10802 (2013.01); H01L 29/7841 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.


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