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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10886222 B1

PDFFull Text
Date of Patent:
Jan. 05, 2021

Filed:

Apr. 10, 2019

Via contact, memory device, and method of forming semiconductor structure

Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Wei Jiang, Hsinchu, TW;

Kuo-Pin Chang, Zhubei, TW;

Chih-Wei Hu, Toufen, TW;

Assignee:

MACRONIX INTERNATIONAL CO., LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Laura M Menz

Assistant Examiner:

Khatib A Rahman

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/11568 (2017.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/31111 (2013.01); H01L 21/76831 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 29/40117 (2019.08); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01);
Abstract

Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

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