The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Apr. 03, 2019
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Yuki Kikuchi, Albany, NY (US);

Kaoru Maekawa, Albany, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/7682 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76834 (2013.01); H01L 21/76885 (2013.01); H01L 21/76831 (2013.01); H01L 21/76843 (2013.01); H01L 21/76871 (2013.01); H01L 21/76883 (2013.01);
Abstract

Self-aligned interconnect patterning for back-end-of-line (BEOL) structures is described. A method of fabricating an interconnect structure for an integrated circuit includes depositing a first metal layer on an initial interconnect structure, forming a patterned spacer layer containing recessed features on the first metal layer, and etching a self-aligned via in the first metal layer and into the initial interconnect structure using a recessed feature in the patterned spacer layer as a mask. The method further includes filling the via in the first metal layer and the recessed features in the patterned spacer layer with a second metal layer, removing the patterned spacer layer, and etching a recessed feature in the first metal layer using the second metal layer as a mask.


Find Patent Forward Citations

Loading…