The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2021
Filed:
Apr. 15, 2019
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Gracieli Posser, Austin, TX (US);
Wing-Kai Chow, Austin, TX (US);
Mehmet Can Yildiz, Austin, TX (US);
Zhuo Li, Austin, TX (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01);
Abstract
Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.