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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10879212 B1

PDFFull Text
Date of Patent:
Dec. 29, 2020

Filed:

Apr. 23, 2018

Processed stacked dies

Applicant:

Invensas Bonding Technologies, Inc., San Jose, CA (US);

Inventors:

Cyprian Emeka Uzoh, San Jose, CA (US);

Guilian Gao, San Jose, CA (US);

Laura Wills Mirkarimi, Sunol, CA (US);

Gaius Gillman Fountain, Jr., Youngsville, NC (US);

Assignee:

Invensas Bonding Technologies, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:

Mounir S Amer

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 21/308 (2006.01); H01L 21/683 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); H01L 21/02076 (2013.01); H01L 21/3085 (2013.01); H01L 21/31116 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/3185 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 21/3065 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/83013 (2013.01); H01L 2224/83031 (2013.01); H01L 2224/83895 (2013.01); H01L 2224/83896 (2013.01);
Abstract

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

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