The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jun. 01, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shu-Uei Jang, Hsinchu, TW;

Chien-Hua Tseng, Hsinchu, TW;

Chung-Shu Wu, Taoyuan, TW;

Ya-Yi Tsai, Hsinchu, TW;

Ryan Chia-Jen Chen, Hsinchu, TW;

An-Chyi Wei, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28123 (2013.01); H01L 21/02156 (2013.01); H01L 21/02186 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of forming a semiconductor device includes removing a top portion of a dielectric layer surrounding a metal gate to form a recess in the dielectric layer; filling the recess with a capping structure; forming a patterned hard mask over the capping structure and over the metal gate, wherein a portion of the metal gate, a portion of the capping structure, and a portion of the dielectric layer are aligned vertically with an opening of the patterned hard mask; and performing an etch process on said portions of the metal gate, the capping structure, and the dielectric layer that are aligned vertically with the opening of the patterned hard mask, wherein the capping structure has an etch resistance higher than an etch resistance of the dielectric layer during the etch process.


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