The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jun. 01, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alaa R. Alameldeen, Hillsboro, OR (US);

Gino Chacon, Longview, TX (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/084 (2016.01); G06F 12/0808 (2016.01); G06F 12/0817 (2016.01); G06F 12/128 (2016.01); G06F 12/0811 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/0813 (2016.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 12/0808 (2013.01); G06F 12/0811 (2013.01); G06F 12/0824 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/128 (2013.01); G06F 12/0813 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/507 (2013.01); G06F 2212/608 (2013.01);
Abstract

Provided are an apparatus and system to cache data in a first cache and a second cache that cache data from a shared memory in a local processor node, wherein the shared memory is accessible to at least one remote processor node. A cache controller writes a block to the second cache in response to determining that the block is more likely to be accessed by the local processor node than a remote processor node. The first cache controller writes the block to the shared memory in response to determining that the block is more likely to be accessed by the one of the at least one remote processor node than the local processor node without writing to the second cache.


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