The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Mar. 28, 2019
Intel Corporation, Santa Clara, CA (US);
Yogesh B. Wakchaure, Folsom, CA (US);
Aliasgar S. Madraswala, Folsom, CA (US);
David J. Pelster, Longmont, CO (US);
Donia Sebastian, Fair Oaks, CA (US);
Curtis Gittens, Vancouver, CA;
Xin Guo, San Jose, CA (US);
Neelesh Vemula, Sunnyvale, CA (US);
Varsha Regulapati, Folsom, CA (US);
Naga Kiranmayee Upadhyayula, Olympia, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.