The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Oct. 09, 2017
Applicant:

Disco Corporation, Tokyo, JP;

Inventors:

Ye Chen, Tokyo, JP;

Frank Wei, Tokyo, JP;

Assignee:

DISCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/26 (2006.01); H05K 3/46 (2006.01); H05K 3/04 (2006.01); B24B 37/04 (2012.01); C25D 5/48 (2006.01); C25D 7/12 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H05K 3/10 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/26 (2013.01); B24B 37/042 (2013.01); C25D 5/48 (2013.01); C25D 7/123 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/562 (2013.01); H05K 3/045 (2013.01); H05K 3/107 (2013.01); H05K 3/465 (2013.01); H05K 3/0044 (2013.01); H05K 2203/025 (2013.01); H05K 2203/0346 (2013.01); Y10T 29/49155 (2015.01);
Abstract

A method for manufacturing a wiring board that has a rewiring layer on a surface thereof includes forming an insulating layer on a core substrate, forming a groove, in which a wiring layer of a circuit pattern is to be provided, on the insulating layer, forming a metal seed layer on an exposed face of the insulating layer on which the groove is formed, electrodepositing metal, which is to form the wiring layer, by plating to fill the groove with the metal to form a metal layer on the seed layer, machining the metal layer by a cutting tool to remove the metal layer up to a position not reaching the top of the insulating layer, and performing etching or a CMP process to expose the top of the insulating layer thereby to form the wiring layer in the groove and flatten an exposed face of the wiring layer.


Find Patent Forward Citations

Chen, Ye. (2020). Manufacturing method for wiring board (U.S. Patent No. 10874021). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10874021

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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