The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Jun. 14, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tsung-Hsueh Yang, Taichung, TW;

Chung-Chiang Min, Hsinchu County, TW;

Chang-Ming Wu, New Taipei, TW;

Shih-Chang Liu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10808 (2013.01); H01L 21/76831 (2013.01); H01L 27/10852 (2013.01); H01L 28/90 (2013.01); H01L 27/1085 (2013.01); H01L 27/10811 (2013.01); H01L 27/10847 (2013.01); H01L 27/10855 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the substrate. A conducting plug is formed in the interlevel dielectric layer. The conducting plug is electrically coupled to the source/drain region. A crown oxide is formed on the interlevel dielectric layer. A deep trench is formed in the crown oxide to expose a top wall and a sidewall of the conducting plug. A spacer is formed on the sidewall of the conducting plug. A metal-insulator-metal film is formed in the deep trench.


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