The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jun. 25, 2019
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Liang Yi, Singapore, SG;

Zhiguo Li, Singapore, SG;

Chi Ren, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7923 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7887 (2013.01);
Abstract

A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.


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