The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Dec. 20, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Su-Jen Sung, Zhubei, TW;

Chih-Chiang Chang, Zhubei, TW;

Chia-Ho Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01); H01L 21/76852 (2013.01); H01L 21/76885 (2013.01); H01L 23/5329 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.


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