The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2020
Filed:
Jul. 19, 2017
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Charlie Zhou, Fremont, CA (US);
Kai-Yuan Ting, San Jose, CA (US);
Sandeep Kumar Goel, Dublin, CA (US);
Tze-Chiang Huang, Sartoga, CA (US);
Yun-Han Lee, Hsinchu County, TW;
Abstract
Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation of various loads on one or more batteries of an electronic device resulting from the electronic device performing one or more functional behaviors. Before this electronic simulation occurs, the electronic device is modeled using the high-level software language or the high-level software format. For example, a battery discharge model, a regulator efficiency model, a power delivery network (PDN) model, or a component power model are used to model behaviors of the one or more batteries, regulator circuitry, power delivery network (PDN) circuitry, and other electronic circuits, respectively, of the electronic device. After completion of the modeling of the electronic device, the ESL design and verification of the present disclosure utilizes a simulation algorithm, in conjunction with the high-level software model of the electronic device to simulate the discharge of electrical energy of the one or more batteries.