The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Nov. 30, 2018
Applicant:

Ningbo Semiconductor International Corporation, Ningbo, CN;

Inventors:

Mengbin Liu, Ningbo, CN;

Hailong Luo, Ningbo, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/48 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06582 (2013.01);
Abstract

A wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure are provided. The method includes providing a device wafer including a first front surface and a first back surface and providing a plurality of second chips. The method also includes forming an adhesive layer on the first front surface and patterning the adhesive layer to form a plurality of first through-holes. In addition, the method includes bonding the plurality of second chips with a remaining adhesive layer to cover the plurality of first through-holes. Moreover, the method includes forming a plurality of second through-holes, which are connected with the plurality of first through-holes to form a plurality of first conductive through-holes, each first conductive through-hole includes a second through-hole and a first through-hole. Further, the method includes forming a first conductive plug in a first conductive through-hole to electrically connect to one of the plurality of second chips.


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