The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Jul. 04, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Yen Tseng, Tainan, TW;

Ching-Cheng Lung, Tainan, TW;

Yu-Tse Kuo, Tainan, TW;

Chun-Hsien Huang, Tainan, TW;

Chih-Wei Tsai, Hsinchu, TW;

Hsin-Chih Yu, Hsinchu County, TW;

Shu-Ru Wang, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01); G11C 15/04 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 15/04 (2013.01); H01L 27/1104 (2013.01);
Abstract

A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.


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