The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Dec. 26, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Binh Pham, Hillsboro, OR (US);
Christopher B. Wilkerson, Portland, OR (US);
Alaa R. Alameldeen, Hillsboro, OR (US);
Zeshan A. Chishti, Hillsboro, OR (US);
Zhe Wang, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0862 (2016.01); G06F 12/0871 (2016.01); G06F 12/1027 (2016.01); G06F 12/0897 (2016.01); G06F 12/1045 (2016.01); G06F 12/128 (2016.01); G06F 12/14 (2006.01); G06F 12/123 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0656 (2013.01); G06F 3/061 (2013.01); G06F 3/0683 (2013.01); G06F 12/0862 (2013.01); G06F 12/0871 (2013.01); G06F 12/0897 (2013.01); G06F 12/1027 (2013.01); G06F 12/1045 (2013.01); G06F 12/128 (2013.01); G06F 12/123 (2013.01); G06F 12/1441 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/60 (2013.01);
Abstract
An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.