The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Sep. 19, 2019
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Hsiao-Chiang Lin, New Taipei, TW;

Chia-Kuang Lee, Hsinchu, TW;

Shih-Ci Yen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 23/544 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/7684 (2013.01); H01L 21/76807 (2013.01); H01L 21/76843 (2013.01); H01L 2223/54426 (2013.01);
Abstract

A method of manufacturing a mark including the following steps is provided. A substrate including a device area and a mark area is provided. A dielectric layer is formed on the substrate. A dual damascene opening is formed in the dielectric layer of the device area. The dual damascene opening includes a first opening and a second opening connected to each other. The width of the second opening is greater than the width of the first opening. A third opening is formed in the dielectric layer of the mark area. The third opening and the first opening are simultaneously formed by the same process. A barrier material layer is formed on the surfaces of the dual damascene opening and the third opening. The barrier material layer seals the third opening to form a void in the third opening. A metal material layer is formed on the barrier material layer.


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