The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jul. 31, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chang-Yin Chen, Taipei, TW;

Chai-Wei Chang, New Taipei, TW;

Bo-Feng Young, Hsinchu, TW;

Yi-Jen Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/32137 (2013.01); H01L 21/762 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 27/0886 (2013.01); H01L 29/42376 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.


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