The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jul. 22, 2016
Applicant:

Hitachi High-technologies Corporation, Tokyo, JP;

Inventors:

Miki Isawa, Tokyo, JP;

Ayumi Doi, Tokyo, JP;

Kazuhisa Hasumi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/28 (2006.01); H01J 37/22 (2006.01); G01N 23/2251 (2018.01); G06T 7/00 (2017.01);
U.S. Cl.
CPC ...
H01J 37/28 (2013.01); G01N 23/2251 (2013.01); G06T 7/001 (2013.01); H01J 37/222 (2013.01); H01J 2237/24578 (2013.01); H01J 2237/2817 (2013.01);
Abstract

A pattern evaluation device has measurement or inspection conditions, supplied for the measurement and inspection of a replica produced by transferring a pattern for a semiconductor wafer or the like, which can be easily set, and with which recipes can be easily generated, when measurement and inspection conditions for the semiconductor wafer or the like and recipes in which these conditions are stored have been prepared in advance. The pattern evaluation device in which a pattern formed on the semiconductor wafer is evaluated on the basis of image data or signal waveforms obtained on the basis of beam irradiation or probe scanning of the semiconductor wafer, wherein the device conditions for evaluating the semiconductor wafer are converted to device conditions for evaluating a replica obtained by transferring a part of a pattern of the semiconductor wafer, and the converted device conditions are used to evaluate the replica.


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