The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Nov. 02, 2018
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Qiang Tang, Cupertino, CA (US);
Ramin Ghodsi, San Jose, CA (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); H03K 19/00 (2006.01); G11C 16/26 (2006.01); H03K 19/0185 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01); G11C 29/50008 (2013.01); H03K 19/0005 (2013.01); H03K 19/018528 (2013.01); G11C 2207/2254 (2013.01);
Abstract
Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.