The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Oct. 05, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Hsien Huang, Tainan, TW;

Ching-Cheng Lung, Tainan, TW;

Yu-Tse Kuo, Tainan, TW;

Shu-Ru Wang, Taichung, TW;

Chun-Yen Tseng, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/11 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/785 (2013.01);
Abstract

A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL) and a gate of a first pull-down device (PD). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL) and a gate of a second pull-down device (PD) and the gate of the PDis directly under the gate of the PD


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