The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Mar. 13, 2017
Applicant:

Shenzhen Xiuyuan Electronic Technology Co., Ltd, Shenzhen, CN;

Inventors:

Chuan Hu, Chandler, AZ (US);

Junjun Liu, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/12 (2006.01); H05K 1/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4864 (2013.01); H01L 21/4867 (2013.01); H01L 21/56 (2013.01); H01L 23/12 (2013.01); H01L 23/3128 (2013.01); H01L 23/4985 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5387 (2013.01); H01L 24/32 (2013.01); H01L 25/0655 (2013.01); H05K 1/00 (2013.01); H01L 24/08 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/3223 (2013.01); H01L 2224/32235 (2013.01); H01L 2224/838 (2013.01); H01L 2224/83013 (2013.01); H01L 2224/83031 (2013.01); H01L 2224/83039 (2013.01); H01L 2224/8385 (2013.01);
Abstract

A chip connection method and structure are provided. The method includes: providing a first connection line and a second connection line on a substrate, wherein, in the thickness direction of the substrate, a distance between the first connection line and the chip is smaller than a distance between the second connection line and the chip; providing the chip on a top surface of the substrate, the chip being provided with at least two chip pins; and providing the substrate with a second through hole corresponding to the second connecting line and provided therein with a second conductive layer, at least one chip pin being electrically connected to the first connection line, and at least one of the remaining chip pin being corresponding to a first opening of the second through, and the second conductive layer electrically connecting the chip pin and the second connection line.


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