The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

May. 17, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Qingqing Liang, San Diego, CA (US);

Peter Graeme Clarke, San Diego, CA (US);

George Pete Imthurn, San Diego, CA (US);

Sinan Goktepeli, San Diego, CA (US);

Sivakumar Kumarasamy, San Diego, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/423 (2006.01); G11C 16/10 (2006.01); H01L 29/66 (2006.01); G11C 16/04 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7887 (2013.01); G11C 16/0408 (2013.01); G11C 16/10 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01);
Abstract

Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.


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