The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2020
Filed:
Feb. 12, 2018
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Assignee:
INFINEON TECHNOLOGIES AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49568 (2013.01); H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49524 (2013.01); H01L 23/49551 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/3107 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48465 (2013.01); H01L 2924/18161 (2013.01);
Abstract
A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.