The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Sep. 11, 2015
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

John Ralph Chase, Brentwood, CA (US);

Mark William Bales, Livermore, CA (US);

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01);
Abstract

In general, embodiments of the present invention provide systems, methods and computer readable media for generating a tiling for a physical placement of a plurality of circuits. The method includes generating a tiling including a plurality of tiles, where each tile identifies a tile geometric area, and a list of one or more of the circuits to be placed in the tile geometric area. The tiling is based on a description of one or more user constraints, where each user constraint identifies a constraint geometric area, and a characteristic of circuits to be placed in the constraint geometric area.


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